... it's really annoying, that the RF12-chip doesn't has a kind
of automatic gain control, thus filling the AVR with interrupts.
A while ago, I did a little investigation on the group 0 garbage. This is what I think happens: When the DQD status bit (data quality detector) is set, the synchron pattern matcher is activated. When the sync byte(s) is/are detected, the FIFO fill starts and you'll receive data. If you take a look at DQD when no signal is transmitted, you'll find that it will very frequently flipper on and off; it will give a lot of false positives. Apparently, this happens so frequently, that it becomes quite probable that (with only one sync byte) the random input matches the sync byte quit frequently as well and thus garbage data is received.
I've tried various RF12 settings to see if I could get DQD to behave more reliably, but everything I tried was worse than the default driver settings. I'm starting to think the DQD function is flawed and you can't get rid of the false positives (or I'm missing something here).
When a transmission is going on, the DQD bit will remain nicely set during the entire transmission (no false negatives) even with very low reveived signal strengths. DQD will stay set even when the the reveived signal is so weak that the crc check fails every time.
This property of DQD can also be used for a goup 0 garbage workaround. You can monitor DQD during reception and if it drops to 0 then abort the reception. You will not risk aborting a valid reception and since DQD fippers quite often you will detect a false reception in a reasonably early stage. This will also work with very weak signals. I actually did a test back then and this approach seemed to work quite well. Also, the DRSSI function remains free to use for other purposes when using DQD instead of DRSSI.
Ofcourse, I should have posted a proper workaround back then, but something else came up and the subject lost my attention...